1. Field of the Invention
The present invention relates to a semiconductor integrated circuit wherein macro cell and standard cells are mixed in, and more particularly to a lay-out structure of power source potential lines and grand potential lines for a semiconductor integrated circuit which is effective for arrangement of these power supply lines between a macro cell and a standard cell by using an automated lay-out technique.
2. Prior Art
In the automated design technique of lay-out for semiconductor integrated circuits wherein macro cell and standard cells are mixed in, a peripheral power supply line is provided manually on the peripheral part of the macro cell in order to connect a power source potential line and a grand potential line to the standard cell and the macro cell.
FIG. 1 is a diagram showing a whole lay-out of such semiconductor integrated circuit according to the prior art wherein a macro cell and standard cells are mixed in. In this semiconductor integrated circuit, a macro cell 30 and a plurality of standard cells 31 are provided.
In the peripheral part of the macro cell 30, a peripheral power supply line 40 and another peripheral power supply line 41 inner thereof are provided. One of these peripheral power supply lines 40 and 41 is used for supply of the power source potential and the other for the grand potential. These peripheral power supply lines 40 and 41 are sufficiently wide to tolerate as the power source potential lines and grand potential lines. Further, all of these peripheral power supply lines 40 and 41 are constituted by first metal layer lines 32 and second metal layer lines 33 which are extending perpendicular to each other. The first metal layer lines 32 is formed by patterning a metal layer on an insulating layer provided on the macro cell 30 and extending toward one direction and the second metal layer lines 33 is formed by patterning a metal layer on an insulating layer provided on the first metal layer line 32 in such a way that the lines 33 extend perpendicular to the first metal layer line 32. The first metal layer line 32 and the second metal layer line 33 are connected through contacts 43.
A plurality of standard cells 31 are arranged laterally to constitute a row of standard cell and a plurality of rows of these standard cells 31 are arranged parallel to each other. Lines 42 supplying power source potential and grand potential to each row of the standard cells 31 are arranged so as to extend perpendicular to the row of the standard cells. These power supply lines 42 are also formed by the second metal layer line 33. Each power supply line 42 formed by the second metal layer line 33 is connected to the manually arranged peripheral power supply lines 40 and 41 which is formed by the first metal layer lines 32 and the second metal layer lines 33, using automated lay-out technique.
FIG. 2 is a lay-out diagram showing enlarged corner part of the macro cell 30. FIG. 2 is an enlarged drawing showing area X indicated by dotted line in FIG. 1. As shown in FIG. 2, power supply lines 44 and 45, power supply lines 46 and 47, or power supply lines 48 and 49 extending laterally are formed by the first metal layer lines 32 for each standard cell row. These power supply lines 44 and 45, 46 and 47 and 48 and 49 are connected to the power supply lines 42 through contacts.
In case the peripheral power supply line 40 is for a power source potential, the peripheral power supply line 41 is for a grand potential, the standard cell power supply lines 44, 46 and 48 are for a power source potential and the standard cell power supply lines 45, 47 and 49 are for a grand potential, the power source lines 44, 46 and 48 must be connected to the outer peripheral power supply line 40 through contacts 43, and the power supply lines 45, 47 and 49 to the inner peripheral power supply line 41 through contacts 43.
When the scale of macro cell 30 is increased, however, the width of peripheral power supply lines 40 and 41 must be expanded accordingly. But, as shown in FIG. 2, if the width of peripheral power supply line 40 is expanded too much to exceed the space between the power supply line 44 supplying the power source potential and the power supply line 45 supplying the grand potential for the standard cell 31, short circuit may occur between the peripheral power supply line 40 of the macro cell 30 and the power supply line 45 of the standard cell 31 at the corner part of the peripheral power supply line 40. That is, the standard cell grand line 45 located nearby the corner part of the peripheral power supply line 40 and the peripheral power supply line 40 for the power source potential may contact each other at the part 35 to form short circuit.
In FIG. 2, the power supply lines 44, 46, 47, 48 and 49 can be connected either to the peripheral power supply line 40 for the power source potential or to the peripheral power supply line 41 for the grand potential by extending straight toward its direction. However, if the power supply line 45 were arranged as it is, the first metal layer line 32 of the peripheral power supply line 40 for the power source potential and the first metal layer line 32 of the power source line 45 for the grand potential, which are formed by patterning the metal layer of the same level, may short each other due to technical limitation of the automated lay-out only allowing extension of the metal line toward one direction.
Therefore, in order to avoid the short circuit formation, as shown in FIG. 3, the first metal layer line 32 is cut off at the connection part of the power supply line 45 with the peripheral power supply line 40. Also, as shown in FIG. 4, the power supply line 45 may be cut off at the same connection part and then the tip of this line 45 and the power supply line 47 for the grand potential which is provided for the adjoining standard cell 31 may be connected by a line 37 using the second metal layer line 33 crossing over the first metal layer line 32 as shown in FIG. 4.
Thus, in the prior art, either cutting off of the line 45 or connecting the line 45 to the line 47 was made to avoid the short circuit formation, in either case the line arrangement was manually modified. Therefore, the line lay-out technique according to the prior art has defect that the line arrangement must be manually modified and the design turn around time (TAT) deteriorates because the line connection is changed after the automated lay-out is completed.